1. Field of the Invention
The present invention relates to a CCD (charge-coupled device) signal read-out circuit, and more particularly to a circuit for reading signals of a CCD used in the form of a solid state image sensor.
2. Description of the Background Art
In a CCD solid state image sensor, electric charges corresponding to signals representative of a line or field of pixels are stored in photo-diodes which are arranged in a linear array or in a matrix configuration pixels thus stored are sequentially transferred to a floating capacitor in a horizontal scanning fashion. The floating capacitor holds the electric charges transferred from the photo-diodes after having cleared the previous charges by applying a reset pulse to the pixels. Those electric charges are developed via a floating diffusion amplifier (FDA) in the form of a CCD signal or a video signal. This signal contains a reset noise (kTC) caused by the floating diffusion amplifier and a fluctuation noise (1/f noise) generated from semiconductor devices included in the floating diffusion amplifier. The noises may be removed by a correlated double sampling circuit (CDS circuit) or a clamp circuit. For the correlated double sampling circuit, there are known, for example, CDS circuits described in Japanese Patent Laid Open Gazette No. 229580/1991, Japanese Utility Model Publication No. 36138/1991 and and Japanese Utility Model Laid Open Gazette No. 66880/1992.
In the correlated double sampling circuit, signal levels during a feed-through period following a reset period in a pixel period are clamped with a clamp pulse, signals during the subsequent pixel signal period are sampled with a sampling pulse. As another correlated doubled sampling circuit, there is one arranged in such a manner that a feed-through period and subsequent signal period are sampled and held, and the resultant outputs are applied to a differential amplifier to cancel the reset noise components. These conventional circuits are described in Japanese Patent Laid Open Publication No. 2295801/1991, for example. Clamping and sampling the signals in this manner brings about mismatch of the signals, which basically contain high frequency noises, with a Nyquist frequency of sampling. As a result, noises lying in a frequency band higher than a frequency equal to one half of the sampling frequency are folded or turned back to the signals. Limitation of the frequency band to a lower band before the correlated double sampling may reduce aliasing noises. However, this involves a distortion of the signal waves and a deterioration of the noise suppression effect by the correlated double sampling. Thus, this causes interference to signals of the adjacent pixels, deterioration of the resolution of the image and color mixture to the adjacent pixels.
Output signals from the solid state image sensor contain also high-frequency noises which are generated from the floating diffusion amplifier and not correlated. However, the high-frequency noises cannot be removed by the correlated double sampling circuit. On the contrary, those noises are folded into the signals owing to the clamping and sample and hold operations of the correlated double sampling circuit. This causes deterioration of an S/N ratio in the system. Hitherto, in order to remove the high-frequency noises, there is adopted an integrator type of sample and hold circuit as disclosed in Japanese Utility Model Publication Nos. 36138/1991 and 66880/1991 referenced above. However, the conventional circuit is complicated in structure and in addition the system needs a higher rate of pulses.